The placement of cells in an IC chip design during development can be summarized as encompassing three stages: During a first stage, the size of the chip is selected and the I/O (input/output) cells are placed. The I/O cells are the cells having pins that connect the chip to the outside world. During a second stage, placement of megacells (such as memories, large blocks of cells, etc.) is accomplished. The third stage comprises the placement of all other cells, such as logic cells, flip-flops, latches, etc. The first two stages are usually referred to as the floorplan development, and the third stage is often referred to as the placement stage.
Integrated circuits are used in a wide range electronic devices produced by a large number of device manufacturers. In practice, ICs are seldom manufactured (fabricated) by the electronic device manufacturer. Instead ICs are manufactured by an IC foundry to the specifications of the electronic device manufacturer. The design of the IC is usually the result of corroboration between the device manufacturer and the IC foundry. Hence, the device manufacturer is a customer to the foundry and the foundry develops the chip for the customer. The first stage of choosing the size of the chip and the placement of its I/O cells is usually performed by the customer to meet the customer's requirements of circuit form, fit and function. The second and third stages are performed by the developer, usually to meet the foundry's processes. In most cases the developer places the megacells manually in accordance with its own heuristic suggestions. Then the developer finishes the process of chip creation using computer tools.
Upon completion of the chip design, the developer decides whether the chip design is acceptable; that is, whether it satisfies certain specifications, such as timing, etc. If it does not, the designer returns to the second stage, remakes the floorplan, and repeats the process until a suitable chip is obtained.
One criterion for determined whether or not a chip design is acceptable is based on the presence or absence of timing violations. The present invention is directed to a process, and to a computer program that causes a computer to carry out the process, for placing megacells during creation of the floorplan to satisfy timing requirements.